# FPGAs: The Ultimate Flex  ## Metadata - Author: [[The Asianometry Newsletter]] - Full Title: FPGAs: The Ultimate Flex - Category: #articles ## Highlights - Field Programmable Gate Array or FPGA is an integrated circuit that can be reprogrammed after manufacture to emulate a digital circuit. These are great for prototyping new functionalities before mass production. Or serving rare use cases that aren't economical for a custom chip. ([View Highlight](https://read.readwise.io/read/01h34q7y54jsvh13dra1cn9pgv)) - Way back in the day, if someone wanted to prototype and test their logic function on some actual hardware, then they largely had just two options. First, they can use TTL chips. These are transistors that you can plug into a printed circuit board. The shortcoming of that approach was that you were limited by the board's size and power consumption limits. The other option would be to get a chip built to order. As you might expect, there are substantial upfront costs with this choice. ([View Highlight](https://read.readwise.io/read/01h34q9t394vvn1f28wxm126vw)) - Today, these customized chips would be called ASICs or Application-Specific Integrated Circuits. It probably does not make economic sense to take this path unless your use case was quite large. ([View Highlight](https://read.readwise.io/read/01h34q9ze2a00pqfb1y7rv229m)) - In 1980, a bunch of engineers formerly from Intel, Signetics, and Intersil founded a design consulting company called Source III. They specialized in helping companies work with their silicon suppliers - a big deal back in a day when design tools weren't amazing. Their experiences working with ASIC chip makers led them to try to make their own field programmable hardware. With that, they raised $750K from a VC and founded a new company - Altera. ([View Highlight](https://read.readwise.io/read/01h34qq3wz1gevnn5gxeepqs7r)) - The big problem with the PAL was that its structure didn't scale. Moore's Law allowed more transistors on the die, but you cannot simply grow the AND-set of gates and get proportionally better performance. It got too large and started slowing down ([View Highlight](https://read.readwise.io/read/01h34qtqew27zq6v6xw6ew1svb)) - If Moore's Law continued, then eventually transistors will get so cheap that it would be possible to make a piece of silicon that met everyone's needs. He recruited a number of Zilog coworkers to join him in his new startup and help realize this dream. They named it Xilinx after their original name Logica had already been taken and officially opened in February 1984. ([View Highlight](https://read.readwise.io/read/01h34r4hneawcec14rtcr0j277)) - To actually design the product, Xilinx hired a young designer named Bill Carter. Carter had a massive challenge ahead of him. The only design guidance they had was the Ross Freeman patent application, a loose description of the idea. Furthermore, Seiko fabbed using a CMOS 2.5 micrometer process, in which Carter had no prior experience. He had to learn it on the fly while communicating with a Japanese-speaking fab across the Pacific. ([View Highlight](https://read.readwise.io/read/01h34r5a5n4kbx9hxhy0m95zp7)) - So if we go back to the PAL, there is a set of AND-gates and a set of OR-gates plus a macro-cell of other circuits like the aforementioned flip flop. The AND-gates are where the chip's field programmability comes from. So as I said earlier, the core problem with the PAL's architecture was that if the AND-set of gates got bigger, then it got slower. That is because the number of transistors inside the set are growing much faster than the number of inputs/outputs on the sides of the AND-set. Those inputs/outputs cannot grow as fast. The FPGA's solution to this shortcoming was to remove the AND-set of gates altogether. In its stead, the FPGA would have an array of configurable logic blocks connected together with programmable switches. ([View Highlight](https://read.readwise.io/read/01h34r8mn0cmf2davrgz1eaqc9)) - Inside each configurable logic block was a pair of look up tables - which is basically like an array of outputs mapped to the inputs. This lookup table is how the FPGA can implement arbitrary logic functions. If necessary, the function result can then be routed to other logics like flip-flops. ([View Highlight](https://read.readwise.io/read/01h34r96y8pna7jawj2s9y9fxt))